1. Field of the Invention
The present invention related generally to the field of non-volatile memory devices, and specifically, to a method and apparatus for increasing the charge retention reliability of such memory devices.
2. Background Information
The advancement of silicon technology calls for aggressive shrinking of a non-volatile memory cell size, especially for electrically erasable programmable read only memory ("EEPROM") devices. There are generally two approaches to shrink the cell size. The first approach is to shrink the physical size of the cell both in the vertical and horizontal dimensions. The second approach is to increase the information density stored in a single cell. For example, to increase the information density of a cell n times, 2.sup.n distinguishable levels in a single cell are required. Instead of one bit per cell, this multi-level approach stores n bit per cell.
The trade-off of such aggressive scaling is the lowering of cell operating reliability due to undesirable floating gate charge loss. While physical scaling results in more charge loss because of its thinner dielectric layer around the floating gate, the multi-level cell operation reduces cell reliability by decreasing the tolerance of the charge loss, since the normal dynamic range is now divided into 2.sup.n distinguishable levels. The more discrete levels a cell is divided into, the narrower the error margin of each level becomes.
One obvious technique to combat the charge loss is to improve process technologies and increase the integrity of insulator layers around the floating gate. However, unless there is a revolutionary technological breakthrough, the data retention characteristics of the cells are unlikely to be improved significantly for a given technology. Since multi-level cell operation puts an extra burden on the charge loss requirement, cell data retention characteristics have emerged as a bottleneck for the multi-level flash technology.
Other techniques used to increase cell data retention margins include increasing the cell operating range by raising the operating voltage and utilizing error correction circuits in a product to detect and correct errors during operation. The drawbacks to the former technique include the increase in chip power consumption and the introduction of serious constrains to device (cell) scaling due to high voltage operation requirements. It may even trigger another charge loss mechanism, namely, read disturb, which will further enhance the total charge loss phenomenon. The disadvantages of the latter technique include longer propagation delays and significant increase in the memory array overhead, or the non-essential memory part of the circuit. This in turn increases the cost of the chip, making device scaling or multi-level cells much less attractive from an economic point of view.